The present invention generally relates to semiconductor devices, and specifically to a structure for detecting defects that may occur while forming back-end-of-the-line structures.
In the manufacture of semiconductor devices, process-induced physical defects in back-end manufacturing processes may cause electrical defects, such as shorts and opens that interfere with device performance and therefore decrease yield. One such process-induced defect is residual material which arises when excess material deposited in back-end structures is not completely removed by a planarization process such as chemical-mechanical planarization (CMP). For example, process-induced defects can occur due to a non-uniform pattern density which leads to a non-uniform polish.
As the dimensions of semiconductor devices have steadily decreased, it has become increasingly difficult to monitor the presence of defects on the devices directly. One approach for addressing these defects has been the fabrication of test structures during the relevant manufacturing process that may be easily examined, either electrically or optically, for defects. The test structures are manufactured at the same time and by the same manufacturing processes, so that by determining defect concentrations on the test structures, it may be possible to approximate the defect concentration of the actual semiconductor devices.
Typically, these test structures are located in the space between the chips (referred to as the kerf) and are not located in the chip area (i.e. not within the chip die) itself. However, defect concentration may not be uniform across a chip. Moreover, some test structures rely on their proximity to the defect source to be able to detect certain kinds of defects. Therefore, it may be advantageous to construct test structure consisting of a potential defect-generating region, a defect-dispersing region and a defect-sensing region that may be located throughout the chip area.